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8816b?dts?12/2012 features ? integrated temperature sensor (ts) + 4-kbit serial eeprom ? jedec jc42.4 (tse2004av) dimm serial presence detect (spd) + ts compliant ? low voltage operation ? optimized for v cc range of 1.7v to 3.6v ? 2-wire serial interface: i 2 c fast mode plus (fm+) compatible ? 100khz, 400khz, and 1mhz compatibility ? bus timeout supported ? schmitt trigger, filtered inputs for noise suppression ? industry standard green (pb/halide-free/rohs compliant) package options ? 8-pad ultra thin dfn (2 x 3 x 0.6mm) ? 8-pad very very thin dfn (2 x 3 x 0.8mm) temperature sensor features ? highly accurate b-grade temp. measurements requiring no external components ? 1.0c accuracy (maximum) over the +75c to +95c range ? 2.0c accuracy (maximum) over the +40c to +125c range ? 3.0c accuracy (maximum) over the -20c to +125c range ? 11-bit adc temperature-to-digital converter with 0.125c resolution ? programmable hysteresis threshold: off, 0c, 1.5c, 3c, and 6c ? low operating current ? temperature sensor active ~0.2ma (typical) serial eeprom features ? integrates 4-kbits of serial eeprom ? internally organized into four quadrants of 128-bytes each ? individual reversible software write protection on all four 128-byte quadrants ? supports byte and page write operations ? self-timed write cycle (5ms maximum) ? high-reliability ? endurance: 1,000,000 write cycles ? data retention: 100 years ? low operating current ? serial eeprom write ~1.5ma (typical) ? serial eeprom read ~0.2ma (typical) atmel at30tse004 integrated temperature sensor with serial eeprom preliminary datasheet not recommended for new designs replaced by at30tse004a
2 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 table of contents 1. description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. pin descriptions and pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. device communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 stop condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 acknowledge (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.4 no-acknowledge (nack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.5 standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.6 device reset and initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.6.1 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4.7 timeout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.8 2-wire software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5. device addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6. temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1 functional description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1.1 event output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.1.2 alarm window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.2.1 pointer register (8-bit write only, address = n/a) . . . . . . . . . . . . . . 13 6.2.2 capability register (16-bit read-only, address = 00h) . . . . . . . . . . 14 6.2.3 configuration register (16-bit read/write, address = 01h) . . . . . . 15 6.2.4 upper limit register (16-bit read/write, address = 02h) . . . . . . . . 18 6.2.5 lower limit register (16-bit read/write, address = 03h) . . . . . . . . 19 6.2.6 critical alarm register (16-bit read/write, address = 04h) . . . . . . 20 6.2.7 temperature register (16-bit read-only, address = 05h) . . . . . . . . 21 6.2.7.1 temperature register format . . . . . . . . . . . . . . . . . . . . 22 6.2.8 manufacturer id register (16-bit read-only, address = 06h) . . . . . 23 6.2.9 device id register (16-bit read-only, address = 07h) . . . . . . . . . . 23 6.3 temperature sensor write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4 temperature sensor read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.4 temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.5 pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8. serial eeprom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.1.1 set page address and read page address commands . . . . . . . . 29 8.2 serial eeprom write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8.2.1 byte write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 8.2.2 page write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2.3 acknowledge (ack) polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2.4 write cycle timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3 write protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.3.1 set rswp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.3.2 clear rswp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.3.3 read rswp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.4 serial eeprom read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.4.1 current address read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.4.2 random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.4.3 sequential read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9. part marking detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 9.1 part markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.1 ordering code detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 11. green package options (pb/halide-free/rohs compliant) . . . . . . 43 12. package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.1 8ma2 ? 8-lead udfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 12.2 8maa ? 8-lead wdfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 13. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 1. description the atmel ? at30tse004 is a combination serial eeprom and temperature sensor device containing 4096-bits of serially electrically erasable and programmable read-only memory (eeprom) organized as 512-bytes of eight bits each. the serial eeprom operation is tailored specifically for dram memory modules with serial presence detect (spd) to store a module?s vital product data such as the module?s size, speed, voltage, data width, and timing parameters. the at30tse004 is protocol compatible with the legacy jedec tse2002av specification (2-kbit) devices enabling the at30tse004 to be utilized in legacy applications without any software changes. the serial eeprom deploys special software commands to allow users to identify and set which half of the memory the internal address counter is located. this special page addressing method used to select the upper or lower half of the serial eeprom is the key to the legacy compatibility. however, there is one minor exception to the legacy compatibility as the at30tse004 does not support the permanent write protection feature because it was removed from the jedec tse2004a (ddr4) specification. in addition, the serial eeprom incorporates a reversible software write protection (rswp) feature enabling the ability to selectively write protect any or all of the four 128-byte quadrants. once the rswp is set, it can only be reversed by sending a special software command sequence. the integrated temperature sensor converts temperatures from -20 ? c to +125 ? c to a digital word and provides an accuracy of 1c (max.) in the temperature range +75 ? c to +95 ? c. the temperature sensor continuously monitors temperature and updates the data in the temperature register at least eight times per second. the temperature data is latched internally by the device and may be read by software via a bus master at anytime (even when the serial eeprom is busy writing data to the memory). the at30tse004 incorporates flexible user programmable internal registers to configure the temperature sensor?s performance and response to over and under temperature conditions. the device contains flexible programmable high, low, and critical temperature limits. the event pin is an active low output and can be configured to operate as an interrupt or as a comparator output. the manufacturer and device id registers provide the ability to confirm the identity of the device. the at30tse004 supports the industry standard 2-wire i 2 c fm plus (fast mode +) serial interface allowing device communication to operate up to 1mhz. a bus timeout feature is supported for both temperature sensor and serial eeprom operations to help prevent system lock-ups. the at30tse004 is available in space saving 8-lead udfn and wdfn packages. the udfn is the recommended and preferred package.
5 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 2. pin descriptions and pinouts table 2-1. pin descriptions figure 2-1. pinout note: udfn is the recommended and preferred package. the metal pad on the bottom of the udfn/wdfn package is not internally connected to a voltage potential. this pad can be a ?no connect? or connected to gnd. symbol name and function asserted state type scl serial clock: the scl pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command and input data present on the sda pin is always latched in on the rising edge of scl, while output data on the sda pin is always clocked out on the falling edge of scl. the scl pin must either be forced high when the serial bus is idle or pulled-high using an external pull-up resistor. ? input sda serial data: the sda pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. the sda pin must be pulled-high using an external pull-up resistor (not to exceed 8k ? in value) and may be wire-ored with any number of other open-drain or open-collector pins from other devices on the same bus. ? input/ output event event: the event pin is an open-drain output pin used to indicate when the temperature goes beyond the user-programmed temperature limits. the event pin can be operated in one of three different modes; either interrupt, comparator, or critical alarm modes. the alert pin must be pulled-high using an external pull-up resistor for proper operation. ? output a 2 , a 1 , a 0 device address inputs: the a 0 , a 1 , and a 2 pins are used to select the device address and corresponds to the three least-significant bits (lsb) of the i 2 c fm+ seven bit slave address. these pins can be directly connected to v cc or gnd in any combination, allowing up to eight devices on the same bus. the a 0 pin is also an overvoltage tolerant pin, allowing up to 10v to support the reversible software write protection (rswp) feature (see section 8.3 ?write protection? on page 35 ). ? input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. ? power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. ? power udfn / wdfn top view a 0 a 1 a 2 gnd v cc event scl sda 8 7 6 5 1 2 3 4
6 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 3. block diagram r o s n e s e r u t a r e p m e t m o r p e e l a i r e s eeprom q uadrant 0 eeprom quadrant 1 eeprom quadrant 2 eeprom quadrant 3 spa = 0, (00h-7fh) spa = 1, (00h-7fh) spa= 1, (80h-ffh) spa = 0, (80h-ffh) 2 a 1 a 0 a d n g v cc event scl sda selected resolution temp. range accuracy event shutdown timeout output feature a/d converter band gap temperature sensor capability configuration critical alarm trip device id manufacturer id temperature upper alarm trip lower alarm trip timeout pointer register h.v pump/timing y address decoder write protect circuitry x address decoder memory control logic serial control logic i 2 c interface
7 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 4. device communication the at30tse004 operates as a slave device and utilizes a simple 2-wire digital serial interface, compatible with the i 2 c fast mode plus (i 2 c fm+) protocol, to communicate with a host controller, commonly referred to as the bus master. the master initiates and controls all read and write operations to the slave devices on the serial bus, and both the master and the slave devices can transmit and receive data on the bus. the serial interface is comprised of just two signal lines: the serial clock (scl) and the serial data (sda). the scl pin is used to receive the clock signal from the master, while the bidirectional sda pin is used to receive command and data information from the master, as well as, to send data back to the master. data is always latched into the at30tse004 on the rising edge of scl and is always output from the device on the falling edge of scl. both the scl and sda pin incorporate integrated spike suppression filters and schmitt triggers to minimize the effects of input spikes and bus noise. all command and data information is transferred with the most-significant bit (msb) first. during the bus communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data has been transferred, the receiving device must respond with either an acknowledge (ack) or a no-acknowledge (nack) response bit during a ninth clock cycle (ack/nack clock cycle) generated by the master. therefore, nine clock cycles are required for every one byte of data transferred. there are no unused clock cycles during any read or write operation so there must not be any interruptions or breaks in the data stream during each data byte transfer and ack or nack clock cycle. during data transfers, data on the sda pin must only change while scl is low, and the data must remain stable while scl is high. if data on the sda pin changes while scl is high, then either a start or a stop condition will occur. start and stop conditions are used to initiate and end all serial bus communication between the master and the slave devices.the number of data bytes transferred between a start and a stop condition is not limited and is determined by the master. in order for the serial bus to be idle, both the scl and sda pins must be in the logic 1 state at the same time. 4.1 start condition a start condition occurs when there is a high-to-low transition on the sda pin while the scl pin is stable in the logic 1 state. the master uses a start condition to initiate any data transfer sequence, and the start condition must precede any command. at30tse004 will continuously monitor the sda and scl pins for a start condition, and the device will not respond unless one is given. please refer to figure 4-1 on page 8 for more details. 4.2 stop condition a stop condition occurs when there is a low-to-high transition on the sda pin while the scl pin is stable in the logic 1 state. the master uses the stop condition to end a data transfer sequence to the at30tse004 which will subsequently return to the idle state. the master can also utilize a repeated start condition instead of a stop condition to end the current data transfer if the master will perform another operation. please refer to figure 4-1 on page 8 for more details. 4.3 acknowledge (ack) after every byte of data is received, at30tse004 must acknowledge to the master that it has successfully received the data byte by responding with an ack. this is accomplished by the master first releasing the sda line and providing the ack/nack clock cycle (a ninth clock cycle for every byte). during the ack/nack clock cycle, the at30tse004 must output a logic 0 (ack) for the entire clock cycle such that the sda line must be stable in the logic 0 state during the entire high period of the clock cycle. please refer to figure 4-1 on page 8 for more details.
8 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 4.4 no-acknowledge (nack) when the at30tse004 is transmitting data to the master, the master can indicate that it is done receiving data and wants to end the operation by sending a nack response to the at30tse004 instead of an ack response. this is accomplished by the master outputting a logic 1 during the ack/nack clock cycle, at which point the at30tse004 will release the sda line so that the master can then generate a stop condition. in addition, the at30tse004 can use a nack to respond to the master instead of an ack for certain invalid operation cases such as an attempt to write to a read-only register (e.g. an attempt to write to the temperature register). figure 4-1. start, stop, and ack 4.5 standby mode the at30tse004 incorporates a low-power standby mode which is enabled: ? upon power-up or ? after the receipt of the stop condition and the completion of any internal operations. 4.6 device reset and initialization the at30tse004 incorporates an internal power-on reset (por) circuit to help prevent inadvertent operations during power-up and power down cycles. on a cold power-up, the supply voltage must rise monotonically between v por(max) and v cc(min) without any ring back to ensure a proper power-up (see figure 4-2 on page 9 ). once the supply voltage has passed the v por(min) threshold, the device?s internal reset process is initiated. completion of the internal reset process occurs within the t init time listed in table 4.6.1 on page 9 . upon completion of the internal reset process, the device will have the following power-on default conditions: ? temperature sensor starts monitoring temperature continuously. ? pointer register = 00h ? upper limit, lower limit, and critical alarm registers are set to 0 ? c. ? event pin is pulled high by the external pull up resistor. ? operational mode is comparator. ? hysteresis level is set to 0 ? c. ? event pin polarity is set low. ? event output is disabled and not asserted. ? serial eeprom?s spa = 0. scl sda sda must be stable sda change allowed sda change allowed acknowledge valid stop condition start condition 12 89 sda must be stable acknowledge window the transmitting device (master or slave) must release the sda line at this point to allow the the receiving device (master or slave) to drive the sda line low to ack the previous 8-bit word. the receiver (master or slave) must release the sda line at this point to allow the transmitter to continue sending new data.
9 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 table 6-1 on page 13 shows the power-on register default values. the upper limit, lower limit, critical alarm, and configuration registers should be programmed to their user desired values before the temperature sensor can properly function. before selecting the device and issuing protocol, a valid and stable supply voltage must be applied and no protocol should be issued to the device for the time specified by the t init parameter. the supply voltage must remain stable and valid until the end of the protocol transmission, and for a serial eeprom write instruction, until the end of the internal write cycle. figure 4-2. power-up timing 4.6.1 power-up conditions do not attempt device access during this time v cc cold power-on reset warm power-on reset v por (max) v cc (min) time t poff t init t por device access permitted v por (min) symbol parameter min max units t por power-on reset time 10.0 ms v por power-up reset voltage range 1.0 1.6 v t init time from power-on to first command 10.0 ms t poff warm power cycle off time 1.0 ms
10 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 4.7 timeout the at30tse004 supports the industry standard bus timeout feature on both temperature sensor and serial eeprom operations to help prevent potential system bus hang-ups. the device resets its serial interface and will stop driving the bus (will let sda float high) if the scl pin is held low for more than the minimum timeout (t out ) specification. the at30tse004 will be ready to accept a new start condition before the maximum t out has elapsed (see figure 4-3 ). this feature does require a minimum scl clock speed of 10khz to avoid any timeout issues. figure 4-3. timeout 4.8 2-wire software reset after an interruption in protocol, power loss, or system reset, any 2-wire part can be reset by following these steps: 1. create a start condition. 2. clock nine cycles. 3. create another start condition followed by stop condition as shown in figure 4-4 . figure 4-4. 2-wire software reset device will release bus and be ready to accept a new start condition within this time t timeout (max) t timeout (min) scl scl sda 9 8 3 2 1 start condition start condition stop condition dummy clock cycles
11 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 5. device addressing the at30tse004 is designed to allow the serial eeprom and the temperature sensor to operate in parallel while executing valid command protocol. for example, when the temperature sensor is busy during a temperature conversion cycle, it is possible to perform any serial eeprom operation during this time and vice versa. the device requires a 7-bit device address and a read/write select bit following a start condition from the master to initiate communication with either the temperature sensor or the serial eeprom. the device address byte is comprised of a 4-bit device type identifier followed by three device address bits (a2, a1,and a0) and a r/ w bit and is clocked by the master on the sda pin with the most significant bit first (see table 5-1 ). the at30tse004 will respond to three unique device type identifiers. the device type identifier of ?1010? (ah) is necessary to select the device for reading or writing. the device type identifier of ?0110? (6h) has multiple purposes. first, it is used to access the page address function which determines what the internal address counter is set to. for more information on accessing the page address function, please refer to section 8.1.1 ?set page address and read page address commands? on page 29 the device type identifier of ?0110? (6h) is also used to access the software write protection feature of the device. information on the software write protection functionality can be found in section 8.3 ?write protection? on page 35 . table 5-1. atmel at30tse004 device address byte the software device address bits (a2, a1, and a0) must match their corresponding hard-wired device address inputs (a 2 , a 1 and a 0 ) allowing up to eight devices on the bus at the same time (see table 5-2 ). the eighth bit of the address byte is the r/ w operation selection bit. a read operation is selected if this bit is a logic 1, and a serial eeprom write operation is selected if this bit is a logic 0. upon a compare of the device address byte, the at30tse004 will output an ack during the ninth clock cycle; if a compare is not true, the device will output a nack during the ninth clock cycle and return the device to the low-power standby mode. table 5-2. device address combinations bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 function device type identifier device address read/write serial eeprom read/write 1 0 1 0 a2 a1 a0 r/ w serial eeprom write protection and page address functions 0 1 1 0 a2 a1 a0 r/ w temperature sensor 0 0 1 1 a2 a1 a0 r/ w software device address bits hard-wired device address inputs a2, a1, a0 a 2 a 1 a 0 0 0 0 gnd gnd gnd 0 0 1 gnd gnd v cc 0 1 0 gnd v cc gnd 0 1 1 gnd v cc v cc 1 0 0 v cc gnd gnd 1 0 1 v cc gnd v cc 1 1 0 v cc v cc gnd 1 1 1 v cc v cc v cc
12 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6. temperature sensor 6.1 functional description the temperature sensor consists of a delta-sigma analog to digital converter (adc) with a band gap type temperature sensor that monitors and updates its temperature measurement at least eight times per second converting the temperature readings into digital data bits and latching them into the temperature register that can be read via the 2-wire i 2 c fm+ serial interface. the device communicates over a 2-wire i 2 c fm+ interface with a master consisting of a serial clock (scl) and a serial bidirectional data bus (sda) with clock frequencies up to 1mhz. the master generates the scl signal and is used by the at30tse004 to receive and send serial data on the sda line with the most significant bit transferred first. a pull-up resistor is required on the sda pin since it has an open drain configuration. 6.1.1 event output the event pin has three operating modes depending on the configuration settings: ? interrupt mode ? comparator mode ? critical alarm (crit_alarm) mode while in interrupt mode, once a temperature reaches a boundary limit, the at30tse004 asserts the event pin. the event pin will remain asserted until the system clears the interrupt by writing a logic 1 to the evtclr bit five in the configuration register. when the temperature drops below specified limits, the device returns back to either interrupt or comparator mode as programmed in the configuration register?s evtmod bit zero. in comparator mode, the event pin remains asserted until the error condition that caused the pin to be asserted no longer exists and the event pin will clear itself. in the crit_alarm mode, when the measured temperature exceeds crit_alarm limit, the event pin will remain asserted until the temperature drops below the crit_alarm limit minus hysteresis (see figure 6-1 on page 17 ). all event thresholds use hysteresis as programmed in the configuration register. 6.1.2 alarm window the alarm window consists of the upper limit register and lower limit register. the upper limit register holds the upper temperature trip point and the lower limit register holds the lower temperature trip point. after the event pin control is enabled, the event output will be triggered upon entering and exiting from this window. 6.2 register descriptions this section describes all the temperature sensor registers that are used in the at30tse004. the at30tse004 contains several registers that are user accessible and/or programmable and utilized for latching the temperature readings, storing high, low, and critical temperature limits, configuring the temperature sensor performance, and reporting temperature sensor status. these registers include a capability register, configuration register, upper limit register, lower limit register, critical alarm register, temperature register, manufacturer identification register, and a device identification/device revision register. the at30tse004 utilizes an 8-bit pointer register to access the 16-bit registers. table 6-1 indicates the write/read access capability for each register. note: reading from a write-only register will result in reading logic 0 data, and writing to a read-only register will have no impact even though the write sequence will be acknowledged by the device.
13 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 table 6-1. registers note: 1. write operations to reserve registers should be avoided as it may cause undesirable results. 6.2.1 pointer register (8-bit write only, address = n/a) the at30tse004 utilizes a pointer register to select and access all the data registers shown on table 6-1 . the pointer register is an 8-bit write only register (see table 6-2 ). the power-on default value is 00h which is the address location for the capability register. table 6-2. pointer register register address read/write section power-on default pointer register n/a w 6.2.1 00h capability register 00h r 6.2.2 00f7h configuration register 01h r/ w 6.2.3 0000h upper limit register 02h r/ w 6.2.4 0000h lower limit register 03h r/ w 6.2.5 0000h critical alarm register 04h r/ w 6.2.6 0000h temperature register 05h r 6.2.7 n/a manufacturer i.d. register 06h r 6.2.8 1114h device i.d./device revision register 07h r 6.2.9 2200h reserved (1) 08h to 0fh r/ w n/a n/a bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 symbol pointer register value r/w w w w w w w w w default value 0 0 0 0 0 0 0 0
14 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6.2.2 capability register (16-bit read-only, address = 00h) this register is a 16-bit read-only register used to specify the functional capabilities of the temperature sensor. the at30tse004 is capable of measuring temperature with 1 ? c over the active range and 2 ? c over the monitor range. the capability register functions are described in table 6-3 and table 6-4 . table 6-3. capability register bit distribution table 6-4. capability register bit description bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 symbol rfu default value 0 0 0 0 0 0 0 0 r/w access r r r r r r r r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 symbol evsd tmout v hv tpres range sacc icap default value 1 1 1 1 0 1 1 1 r/w access r r r r r r r r bit symbol description 15:8 rfu reserved for future use and must be logic 0. 7 evsd event output status during shutdown mode : 1 = the event pin output is deasserted (not driven) when entering shutdown mode and will remain deasserted upon exit from shutdown mode until the next temperature measurement sample is taken. in interrupt mode, the event pin maybe asserted when existing shutdown if a pending interrupt has not be cleared. 6 tmout timeout: 1 = bus timeout supported within the range 25 to 35ms. 5 v hv high voltage support for a 0 pin: 1 = the a 0 pin supports a maximum voltage up to 10v. 4:3 tpres temperature resolution: 10 = supports 0.125 ? c (11-bit resolution). 2 range 1 = can read temperatures below 0c and sets appropriate sign bit. 1 sacc supported accuracy: 1 = supports a b-grade accuracy of 1 ? c over the active range (75 ? c to 95 ? c) and 2 ? c over the monitor range (40 ? c to 125 ? c). 0 icap interrupt capability: 1 = supports interrupt capabilities.
15 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6.2.3 configuration register (16-bit read/write, address = 01h) the at30tse004 incorporates a 16-bit configuration register allowing the user to set key operational features of the temperature sensor. the configuration register functions are described in table 6-5 and table 6-6 . table 6-5. configuration register bit distribution bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 symbol rfu hystenb shtdwn default value 0 0 0 0 0 0 0 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 symbol crtalml winlock evtclr evtsts evtout critevt evtpol evtmod default value 0 0 0 0 0 0 0 0 r/w access r/w r/w w r r/w r/w r/w r/w table 6-6. configuration register bit description bit symbol description 15:11 rfu reserved for future use and must be logic 0. 10:9 hystenb hysteresis enable: 00 = 0 ? c disable hysteresis (power-on default) 01 = 1.5 ? c enable hysteresis 10 = 3.0 ? c enable hysteresis 11 = 6.0 ? c enable hysteresis the purpose of these bits is to control the hysteresis applied to the temperature limit trip point boundaries. the above hysteresis applies to all limits when temperature drops below the user specified temperature limit trip points. note: hysteresis applies to decreasing temperature only. once the temperature is above a given threshold, the temperature must drop below the boundary limit minus hysteresis in order for a comparator event to be cleared. example: if these two bits are set to ?01? for 1.5 ? c and the upper limit is set to 85 ? c, as temperature rises above 85 ? c, bit 14 of the temperature register will be set to a logic 1. bit 14 will remain set until the temperature drops below the threshold (85 ? c) minus the hysteresis value(83.5 ? c). note: hysteresis is also applied to the event pin functionality. this bit cannot be changed if the crit_alarm or alarm window lock bits is set. 8 shtdwn shutdown mode: 0 = the temperature sensor is enabled for continuous conversion (power-on default). 1 = the temperature sensor is disabled. to save power in shutdown mode, the temperature sensor is not active and will not generate interrupts or update the temperature data. the event pin is deasserted (not driven). this bit cannot be set to a logic 1 if either of the crit_alarm or alarm window lock bits is set, however, it can be cleared at any time. the device will respond to protocol commands and the bus timeout is active when in shutdown mode.
16 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 7 crtalml crit_alarm lock bit: 0 = the crit_alarm register can be updated (power-on default). 1 = the crit_alarm register is locked and cannot be updated. this bit locks the critical alarm register from being updated. once set, it can only be cleared to a logic 0 by an internal power-on reset. 6 winlock alarm window lock bit: 0 = the upper limit and lower limit registers can be updated (power-on default). 1 = the upper and lower limit registers are locked and cannot be updated. once set, it can be only be cleared to a logic 0 by an internal power-on reset. 5 evtclr event clear: 0 = has no effect (power-on default). 1 = clears (releases) the active event pin in interrupt mode. this bit will clear the event pin after it has been enabled. this bit is a write-only bit and will read as a logic 0 and is ignored when in comparator mode. 4 evtsts event pin output status: 0 = the event output is not asserted by the device (power-on default). 1 = the event output is asserted due to a limit or alarm condition. 3 evtout event output control: 0 = the event output is disabled and will not generate interrupts (power-on default). 1 = the event output is enabled. this bit cannot be altered if the crit_alarm or the alarm window lock bits is set. 2 critevt critical temperature only: 0 = the event output is asserted if the measured temperature is above the upper limit or critical alarm, or is below the lower limit (power-on default). 1 = the event output is asserted only for a critical alarm violation when the temperature is greater then the crit_alarm. this bit cannot be altered if the alarm window lock bit is set. 1 evtpol event polarity: 0 = the event pin is active low (power-on default). 1 = the event pin is active high. this bit cannot be altered if the crit_alarm or the alarm window lock bit is set. a pull-up resistor is required on this pin to achieve the logic 1 state. 0 evtmod event mode: 0 = the event pin will operate in comparator mode (power-on default). 1 = the event pin will operate in interrupt mode. this bit cannot be altered if the crit_alarm or the alarm window lock bit is set. table 6-6. configuration register bit description (continued) bit symbol description
17 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 figure 6-1. event pin mode functionality crit_alarm upper limit measured temperature lower limit event pin in ?interrupt mode? (active low) event pin in ?crit_alarm only mode? (active high) event pin in ?comparator mode? (active low) software resets interrupt switches to comparator mode
18 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6.2.4 upper limit register (16-bit read/write, address = 02h) the upper limit register holds the user programmed upper temperature boundary trip point in 2?s complement format (0.125 ? c resolution) that can be utilized to monitor the temperature in an operating window between the upper limit register and the lower limit register settings (see table 6-7 and table 6-9 ). when the temperature increases above this trip point, drops below, or is equal to the trip point (minus any hysteresis set), then the event pin is asserted (if enabled). this register is read-only if the alarm window lock (winlock) bit six in the configuration register is set to a logic 1. table 6-7. upper limit register bit distribution table 6-8. upper limit register bit description bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 symbol rfu sign almwinh default value 0 0 0 0 0 0 0 0 r/w access r r r r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 symbol almwinh rfu default value 0 0 0 0 0 0 0 0 r/w access r/w r/w r/w r/w r/w r/w r r bit symbol description 15:13 rfu reserved for future use . read as logic 0. 12 sign sign bit: 0 = the temperature is greater than or equal to 0c. 1= the temperature is less than 0c. 11:2 almwinh upper limit temperature bits: represented in 2?s complement format. read-only access if alarm window is locked (configuration register bit 6 high). r/w access if the alarm window is unlocked. 0:1 rfu reserved for future use . read as logic 0.
19 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6.2.5 lower limit register (16-bit read/write, address = 03h) the lower limit register holds the user programmed lower temperature boundary trip point in 2?s complement format (0.125 ? c resolution) that can be utilized to monitor the temperature in an operating window (see table 6-7 and table 6-9 ). when the temperature decreases below this trip point minus any hysteresis set or increases to meet or exceed this trip point, then the event pin is asserted (if enabled). this register becomes read-only if the alarm window lock (winlock) bit six in the configuration register is set to a logic 1. table 6-9. lower limit register bit distribution table 6-10. lower limit register bit description bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 symbol rfu sign almwinl default value 0 0 0 0 0 0 0 0 r/w access r r r r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 symbol almwinl rfu default value 0 0 0 0 0 0 0 0 r/w access r/w r/w r/w r/w r/w r/w r r bit symbol description 15:13 rfu reserved for future use . read as logic 0. 12 sign sign bit: 0 = the temperature is greater than or equal to 0c. 1 = the temperature is less than 0c. 11:2 almwinl lower limit temperature bits: represented in 2?s complement format. read-only access if alarm window is locked (configuration register bit 6 high). r/w access if the alarm window is unlocked. 0:1 rfu reserved for future use . read as logic 0.
20 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6.2.6 critical alarm register (16-bit read/write, address = 04h) the critical alarm register holds the user programmed critical alarm temperature boundary trip point in 2?s complement format (0.125c resolution) that can be utilized to monitor the temperature (see table 6-11 and table 6-12 ). when the temperature increases above this trip point, the event pin will be asserted (if enabled). it will remain asserted until temperature decreases below or equal to the trip point minus any hysteresis set. this register becomes read-only if the critical alarm lock bit (crtalml) bit seven in the configuration register is set to a logic 1. table 6-11. critical alarm register bit distribution table 6-12. critical alarm register bit description bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 symbol rfu sign critevt default value 0 0 0 0 0 0 0 0 r/w access r r r r/w r/w r/w r/w r/w bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 symbol critevt rfu default value 0 0 0 0 0 0 0 0 r/w access r/w r/w r/w r/w r/w r/w r r bit symbol description 15:13 rfu reserved for future use . read as logic 0. 12 sign sign bit: 0 = the temperature is greater than or equal to 0c. 1 = the temperature is less than 0c. 11:2 critevt critical alarm temperature bits: represented in 2?s complement format. read-only access if alarm window is locked (configuration register bit 6 high). r/w access if the alarm window is unlocked. 0:1 rfu reserved for future use . read as logic 0.
21 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6.2.7 temperature register (16-bit read-only, address = 05h) the temperature register holds the internal temperature measurement data represented in 2?s complement format allowing for resolution equal to 0.125 ? c (least significant bit). the upper three bits (15, 14, and 13) of the temperature register indicates the trip status of the current temperature and most important, are not affected by the status of the output of the event pin (see table 6-13 and table 6-14 ). table 6-13. temperature register bit distribution table 6-14. temperature register bit description bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 symbol crithigh almhigh almlow sign 128c 64c 32c 16c default value 0 0 0 0 0 0 0 0 r/w access r r r r r r r r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 symbol 8c 4c 2c 1c 0.5c 0.25c 0.125c rfu default value 0 0 0 0 0 0 0 0 r/w access r r r r r r r r bit symbol description 15 crithigh 0 = the temperature is less than the critical alarm register setting. 1 = the temperature is greater than or equal to critical alarm register setting. when this bit is set to a logic 1, it will automatically clear once the measured temperature decreases below or is equal to the trip point minus any hysteresis set. 14 almhigh 0 = the temperature is below the upper limit register setting. 1 = the temperature is above the upper limit register setting. when the bit is set to a logic 1, it will automatically clear once the measured temperature decreases below or is equal to the trip point minus any hysteresis set. 13 almlow 0 = the temperature is above the lower limit register setting. 1 = the temperature is below the lower limit register setting. when the bit is set to a logic 1, it will automatically clear once the measured temperature increases above or is to equal to the trip point. 12 sign sign bit: 0 = the temperature is greater than or equal to 0c. 1 = the temperature is less than 0c. 11:1 temp temperature bits: represented in 2?s complement format. the encoding of bits b11 through b2 is the same as in the limit and alarm registers. 0 rfu reserved for future use . read as logic 0.
22 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6.2.7.1 temperature register format this section will clarify the temperature register format and temperature bit value assignments utilized for temperature for the following registers: upper limit, lower limit, critical alarm, and temperature registers. the temperatures expressed in the upper limit, lower limit, critical alarm, and temperature registers are indicated in 2?s complement format. in each of the temperature limit registers, bits 12 through bit two are utilized for temperature settings, or in the case of the temperature register, holds the internal temperature measurement with bits 12 through bit one allowing 0.125oc resolution. table 6-15 indicates the temperature register?s assigned bit values utilized for temperature and shows examples for the temperature register bit values for various temperature readings. table 6-15. temperature register format table 6-16. temperature register examples position bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit value sign 128c 64c 32c 16c 8c 4c 2c 1c 0.5c 0.25c 0.125c x temperature register value examples temperature binary (bit 15 ? bit 0) +125c xxx0 0111 1101 00xx +99.75c xxx0 0110 0011 11xx +85c xxx0 0101 0101 00xx +39c xxx0 0010 0111 00xx +15.75c xxx0 0000 1111 11xx +0.25c xxx0 0000 0000 01xx 0c xxx0 0000 0000 00xx -0.25c xxx1 1111 1111 11xx -1c xxx1 1111 1110 00xx -20c xxx1 1110 1100 00xx
23 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6.2.8 manufacturer id register (16-bit read-only, address = 06h) the manufacturer id register contains the pci sig number assigned to atmel (1114h) as shown in table 6-17 . table 6-17. manufacturer id register bit distribution 6.2.9 device id register (16-bit read-only, address = 07h) the upper or high order byte is used to specify the device identification and the low byte is used to specify the device revision. the device id for the at30tse004 is 2200h (see table 6-18 ). table 6-18. device id register bit distribution bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 symbol manufacturer id default value 0 0 0 1 0 0 0 1 r/w access r r r r r r r r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 symbol manufacturer id default value 0 0 0 1 0 1 0 0 r/w access r r r r r r r r bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 symbol device id default value 0 0 1 0 0 0 1 0 r/w access r r r r r r r r bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 symbol device revision default value 0 0 0 0 0 0 0 0 r/w access r r r r r r r r
24 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6.3 temperature sensor write operations writing to the at30tse004?s temperature register is accomplished through a modified write operation for two data bytes. to maintain 2-wire compatibility, the 16-bit registers are accessed through a pointer register requiring the ts write sequence to include a pointer register byte following the device address byte to write the two data bytes. figure 6-2 illustrates the entire write transaction. figure 6-2. temperature sensor register write operation scl sda start by master ack from slave ack from slave device address byte pointer register byte msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 0 1 1 a2 a1 a0 0 0 0 start by master ack from slave ack from slave most significant data byte least significant data byte stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 0 p7 p6 p5 p4 p3 p2 p1 p0
25 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 6.4 temperature sensor read operations reading data from the temperature sensor may be accomplished in one of two ways: ? if the location latched in the pointer register is correct (for normal operation, it is expected the same address will be read repeatedly to read the temperature from the temperature register), the register pointer word read sequence should be utilized as shown in figure 6-3 . to perform a register pointer word read, the master transmits a start condition followed by a device address byte with the r/ w select bit to a logic 1. the at30tse004 should respond with an ack and will transmit the most significant data byte. the master should send an ack followed by the device transmitting the least significant data byte. to end the read operation, the master sends a nack followed by a stop condition. ? if it is desired to read a random register or simply change to read a different register from the temperature sensor, then the preset pointer register word read protocol sequence should be followed and is shown in figure 6-4 . the preset pointer register word read sequence allows the pointer register to be preloaded with the correct register address to gain access to the desired register to be read. to perform a preset pointer register word read, the master transmits a start condition followed by a device address byte (with the r/ w select bit to a logic 0) and a pointer register byte to the at30tse004. once the device address and pointer register bytes are clocked in and acknowledged by the at30tse004, the master must generate another start condition. the master transmits another device address byte (with the r/ w select bit to a logic 1) followed by an ack by the at30tse004 and the device transmitting the most significant data byte. the master should send a ack followed by the device transmitting the least significant data byte. to end the read operation, the master should send a nack followed by a stop condition. figure 6-3. register pointer word read figure 6-4. preset pointer register word read sck sda start by master ack from slave nack from master stop by master ack from master device address byte most significant data byte least significant data byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 0 1 1 a2 a1 a0 1 0 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 1 msb msb msb scl sda start by master start by master ack from slave ack from slave device address byte pointer register byte msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 0 1 1 a2 a1 a0 0 0 0 ack from slave device address byte msb 1 2 3 4 5 6 7 8 9 0 0 1 1 a2 a1 a0 1 0 nack from master ack from master most significant data byte least significant data byte stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 1 p7 p6 p5 p4 p3 p2 p1 p0
26 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 7. electrical specifications 7.1 absolute maximum ratings* 7.2 dc characteristics applicable over recommended operating range: t a = ?20c to +125c, v cc = 1.7v to 3.6v (unless otherwise noted). notes: 1. v il min and v ih max are reference only and are not tested. 2. ts in shutdown mode. 3. serial eeprom inactive, ts in shutdown mode. operating temperature . . . . . . . . . . - 40c to +125c storage temperature . . . . . . . . . . . - 65c to +150c voltage on any pin with respect to ground . . . . . . . . . . . . . . - 1.0v to 5.0v pin a 0 . . . . . . . . . . . . . . . . . . . . . . . . . . - 1.0v to 12.0v maximum operating voltage . . . . . . . . . . . . . . . . 4.3v dc output current. . . . . . . . . . . . . . . . . . . . . . . 5.0ma *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification are not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol parameter test condition min typ max units v cc supply voltage 1.7 3.6 v i cc1 supply current (2) v cc = 3.6v read at 100khz 0.4 1.0 ma i cc2 supply current (2) v cc = 3.6v write at 100khz 1.5 3.0 ma i cc3 temp sensor v cc = 3.6v ee inactive 0.2 0.5 ma i sb standby current (3) v cc = 1.7v v in = v cc or v ss 1.6 3.0 a v cc = 3.6v v in = v cc or v ss 1.6 4.0 a i li input leakage current v in = v cc or v ss 0.1 2.0 a i lo output leakage current v out = v cc or v ss 0.1 2.0 a v il input low level (1) -0.5 0.3 * v cc v v ih input high level (1) 0.7 * v cc v cc + 0.5 v v ol1 low-level output voltage open-drain v cc > 2v i ol = 3ma 0.4 v v ol2 v cc 2v i ol = 2ma 0.2 * v cc v i ol low-level output current v ol = 0.4v freq 400khz 3.0 ma v ol = 0.6v freq 400khz 6.0 ma v ol = 0.4v freq > 400khz 20.0 ma v hyst1 input hysteresis (sda, scl) v cc < 2v 0.10 * v cc v v hyst2 input hysteresis (sda, scl) v cc 2v 0.05 * v cc v
27 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 7.3 ac characteristics notes: 1. this parameter is ensured by characterization only. 2. the minimum frequency is specified at 10khz to avoid activating the timeout feature. figure 7-1. scl: serial clock, sda: serial data i/o applicable over recommended operating range: t a = ?20c to +125c, v cc = 1.7v to 3.6v, cl = 1 ttl gate and 100 f (unless otherwise noted). symbol parameter v cc < 2.2v v cc 2.2v units 100khz 400khz 1000khz min max min max min max f scl clock frequency, scl 10 (2) 100 10 (2) 400 10 (2) 1000 khz t low clock pulse width low 4700 1300 500 ns t high clock pulse width high 4000 600 260 ns t i noise suppression time 50 50 50 ns t buf time the bus must be free before a new transmission can start (1) 4700 1300 500 ns t hd.sta start hold time 4000 600 260 ns t su.sta start set-up time 4700 600 260 ns t hd.di data in hold time 0 0 0 ns t su.dat data in set-up time 250 100 50 ns t r inputs rise time (1) 1000 20 300 120 ns t f inputs fall time (1) 300 20 300 120 ns t su.sto stop set-up time 4000 600 260 ns t hd.dat data out hold time 200 3450 200 900 0 350 ns t wr write cycle time 5 5 5 ms t out timeout time 25 35 25 35 25 35 ms eeprom write endurance 25c, page mode (1) 1,000,000 write cycles scl sda t f t high t low t low t r t buf t su.sto t su.dat t hd.dat t hd.sta t su.sta
28 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 7.4 temperature sensor characteristics 7.5 pin capacitance (1) note: 1. this parameter is ensured by characterization only. applicable over recommended operating range: t a = ?20c to +125c, v cc = 1.7v to 3.6v (unless otherwise noted). symbol parameter test condition freq. 400khz freq. > 400khz unit s min typ max min typ max t acc ts accuracy (b-grade) +75c < t a < +95c 0.5 1.0 0.5 1.0 c +40c < t a < +125c 1.0 2.0 1.0 2.0 c -20c < t a < +125c 2.0 3.0 2.0 3.0 c t conv ts conversion time 75.0 125.0 75.0 125.0 ms t res ts resolution 0.125 0.125 c applicable over recommended operating range from t a = +25c, f = 1mhz, v cc = 1.7v - 3.6v. symbol test condition max units conditions c i/o input/output capacitance (sda, event) 8 pf v i/o = 0v c in input capacitance (a 0 , a 1 , a 2 , scl) 6 pf v in = 0v
29 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8. serial eeprom 8.1 memory organization to provide the greatest flexibility and backwards compatibility with the previous generations of spd devices, the at30tse004 memory organization is organized into two independent 2-kbit memory arrays. each 2-kbit (256-byte) section is internally organized into two independent quadrants of 128 bytes with each quadrant comprised of eight pages of 16 bytes. including both memory sections, there are four 128-byte quadrants totaling 512 bytes. the memory array organization details are shown in section 3. on page 6 and table 8-1 . 8.1.1 set page address and read page address commands the at30tse004 incorporates an innovative memory addressing technique that utilizes a set page address (spa) and read page address (rpa) commands to select and verify the desired half of the memory is enabled to perform write and read operations. example: if spa = 0, then the first-half or lower 256 bytes of the serial eeprom is selected allowing access to quadrant 0 and quadrant 1. alternately, if spa = 1, then the second-half or upper 256 bytes of the serial eeprom is selected allowing access to quadrant 2 and quadrant 3 . table 8-1. set page address and memory organization note: due to the requirement for the a0 pin to be driven to v hv , the spa and the rpa commands are fully supported in a single dimm (isolated dimm) end application or a single dimm programming station only. setting the set page address (spa) value selects the desired half of the eeprom for performing write or read operations. this is done by sending the spa as seen in figure 8-1 . the spa command sequence requires the master to transmit a start condition followed by sending a control byte of ?011011*0? where the ?*? in the bit 7 position will dictate which half of the eeprom is being addressed. a ?0? in this position (or 6ch) is required to set the page address to the first half of the memory and a ?1? (or 6eh) is necessary to set the page address to the second half of the memory. after receiving the control byte, the at30tse004 should return an ack and the master should follow by sending two data bytes of don?t care values. the at30tse004 responds with a nack to each of these two data bytes although the jedec tse2004av specification allows for either an ack or nack response. the protocol is completed by the master sending a stop condition to end the operation. block set page address (spa) memory address locations quadrant 0 0 00h to 7fh quadrant 1 0 80h to ffh quadrant 2 1 00h to 7fh quadrant 3 1 80h to ffh
30 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 figure 8-1. set page address (spa) reading the state of the spa can be accomplished via the read page address (rpa) command. the master can issue the rpa command to determine if the at30tse004?s internal address counter is located in the first 2-kbit section or the second 2-kbit memory section based upon the device?s ack or nack response to the rpa command. the rpa command sequence requires the master to transmit a start condition followed by a control byte of ?01101101? (6dh). the device?s current address counter (page address) is located in the first half of the memory if the at30tse004 responds with an ack to the rpa command. alternatively, if the device?s response to the rpa command is a nack, indicates the page address is located in the second half of the memory (see figure 8-2 ). following the control byte and the device?s ack or nack response, the at30tse004 should transmit two data bytes of don?t care values. the master should nack on these two data bytes followed by the master sending a stop condition to end the operation. after power-up, the spa is set to zero indicating internal address counter is located in the first half of the memory. performing a software reset (see section 4.8 ?2-wire software reset? on page 10 ) will also set the spa to zero. the at30tse004 incorporates a reversible software write protect (rswp) feature that allows the ability to selectively write protect data stored in any or all of the four serial eeprom 128-byte quadrants. see section 8.3 ?write protection? on page 35 for more information on the rswp feature. figure 8-2. read page address (rpa) scl sda start by master ack from slave nack from slave stop by master nack from slave control byte most significant data byte least significant data byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 1 1 0 1 1 * 0 0 x x x x x x x x 1 x x x x x x x x 1 msb msb msb bit * = 1: indicates the page address is located in the second half of the memory. bit * = 0: indicates the page address is located in the first half of the memory. scl sda start by master ack or nack from slave nack from master stop by master nack from master control byte most significant data byte least significant data byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 1 1 0 1 1 0 1 * x x x x x x x x 1 x x x x x x x x 1 msb msb msb bit * = 1: nack indicates the device?s internal address counter is located in the second half of the memory. bit * = 0: ack indicates the device?s internal address counter is located in the first half of the memory.
31 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8.2 serial eeprom write operations the 4-kbit serial eeprom within the at30tse004 supports single byte write and page write operations up to the maximum page size of 16 bytes in one operation. the only difference between a byte write and a page write operation is the amount of data bytes loaded. regardless of whether a byte write or page write operation is performed, the internally self-timed write cycle will take the same amount of time to write the data to the addressed memory location(s). temperature sensor operations can be accessed during the write cycle to read the temperature register or perform any other temperature sensor function. caution: all byte write and page write operations should be preceded by the spa and or rpa commands to ensure the internal address counter is located in the desired half of the memory. if a byte write or page write operation is attempted to a protected quadrant, then the at30tse004 will respond (ack or nack) to the write operation according to table 8-2 . table 8-2. serial eeprom acknowledge status when writing data or defining write protection quadrant status instruction sent instruction response word address sent word address response data word sent data word response write cycle write protected with set rswp set rswp nack don?t care nack don?t care nack no clear rswp ack don?t care ack don?t care ack yes byte write or page write to protected quadrant ack word address ack data nack no not protected set rswp or clear rswp ack don?t care ack don?t care ack yes byte write or page write ack word address ack data ack yes
32 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8.2.1 byte write following the start condition from the master, the device type identifier (?1010?) , the device address bits and the r/ w select bit (set to a logic 0) are clocked onto the bus by the master (see figure 8-3 ). this indicates to the addressed device that the master will follow by transmitting a byte with the word address. the at30tse004 will respond with an ack during the ninth clock cycle. then the next byte transmitted by the master is the 8-bit word address of the byte location to be written into the serial eeprom. after receiving an ack from the at30tse004, the master transmits the data word to be programmed followed by an ack from the at30tse004. the master ends the write sequence with a stop condition during the 10 th clock cycle to initiate the internally self-timed write cycle. a stop condition issued during any other clock cycle during the write operation will not trigger the internally self-timed write cycle. once the write cycle begins, the pre-loaded data word will be programmed in the amount of time not to exceed the t wr specification. the t wr time is defined in more detail in section 8.2.4 on page 34 . during this time, the master should wait a fixed amount of time set to the t wr specification, or for time sensitive applications, an ack polling routine can be implemented (see figure 8-5 on page 34 ). all inputs are ignored by the serial eeprom during the write cycle and the serial eeprom will not respond until the write cycle is complete. the serial eeprom will increment its internal address counter each time a byte is written. note: the temperature sensor operations can be accessed during the write cycle to read the temperature register or perform any other temperature sensor function. figure 8-3. byte write to serial eeprom scl sda device address byte word address byte data word start by master ack from slave ack from slave msb msb ack from slave stop by master msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a2 a1 a0 0 0 a7 a6 a5 a4 a3 a2 a1 a0 0 d7 d6 d5 d4 d3 d2 d1 d0 0
33 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8.2.2 page write the 4-kbit serial eeprom is capable of writing up to 16 data bytes at a time executing the page write protocol sequence (see figure 8-4 ). a partial or full page write operation is initiated the same as a byte write operation except that the master does not send a stop condition after the first data word is clocked in. instead, after the serial eeprom has acknowledged receipt of the first data word, the master can transmit up to fifteen more data words. the device will respond with an ack after each data word is received. the lower four bits of the data word address are internally incremented following the receipt of each data word. the higher data word address bits are not incremented, retaining the memory page row location. when the internally generated word address reaches the page boundary, then the following data word is placed at the beginning of the same page. if more than sixteen data words are transmitted to the serial eeprom, the data word address will roll-over and the previous data will be overwritten. the address roll-over during a write sequence is from the last byte of the current page to the first byte of the same page. the master ends the page write sequence with a stop condition during the 10th clock cycle to initiate the internally self- timed write cycle. a stop condition issued during any other clock cycle during the write operation will not trigger the internally self-timed write cycle. once the write cycle begins, the pre-loaded data words will be programmed in the amount of time not to exceed the t wr specification. all inputs are ignored by the serial eeprom during the write cycle and the serial eeprom will not respond until the write cycle is complete. the t wr time is defined in more detail in section 8.2.4 on page 34 . during this time, the master should wait a fixed amount of time set to the t wr specification, or for time sensitive applications, an ack polling routine can be implemented (see figure 8-5 on page 34 ). figure 8-4. page write to serial eeprom scl sda start by master ack from slave ack from slave device address byte word address byte msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a2 a1 a0 0 0 0 ack from slave ack from slave stop by master ack from slave data word (n) data word (n+1) data word (n+15) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 msb msb msb a7 a6 a5 a4 a3 a2 a1 a0
34 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8.2.3 acknowledge (ack) polling an ack polling routine can be implemented to optimize time sensitive applications that would not prefer waiting the fixed maximum write cycle time and would prefer to know immediately when the serial eeprom write cycle has completed to start a subsequent operation. once the internally self timed write cycle has started (the stop condition during the 10 th clock cycle at the end of the write sequence), the serial eeprom inputs are disabled and ack polling can be initiated (see figure 8-5 ). an ack polling routine involves sending a valid start condition followed by the device address byte. while the write cycle is in progress, the device will not respond with an ack indicating the serial eeprom is busy writing data. once complete, the device will ack and the next device operation can be started. note: the temperature sensor operations can be accessed during the write cycle to read the temperature register or perform any other user desired temperature sensor operation. figure 8-5. acknowledge polling flow chart 8.2.4 write cycle timing the length of the self timed write cycle, or t wr , is defined as the amount of time from a valid stop condition that begins the internal write sequence to the start condition of the first device address byte sent to the at30tse004 that it subsequently responds to with an ack. figure 8-6 has been included to show this measurement. figure 8-6. write cycle timing did the device ack? send any write protocol send stop condition to initiate write cycle send start condition followed by valid device address byte continue to next operation no yes t wr stop condition start condition data word n ack d0 sda stop condition scl 89 ack first acknowledge from the device to a valid device address sequence after write cycle is initiated. the minumum t wr can only be determined through the use of an ack polling routine. 9
35 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8.3 write protection the at30tse004 incorporates a reversible software write protection (rswp) feature that allows the ability to selectively write protect data stored in each of the four independent 128-byte serial eeprom quadrants. table 8-3 identifies the memory quadrant identifier with its associated quadrant, spa and memory address locations. the at30tse004 has three rswp software commands: ? set rswp command for setting the rswp. ? clear rswp command for resetting all of the quadrants that are software write protected. ? read rswp command for reading the rswp status. table 8-3. serial eeprom memory organization block spa address locations memory quadrant identifier quadrant 0 0 00h to 7fh 001 quadrant 1 0 80h to ffh 100 quadrant 2 1 00h to 7fh 101 quadrant 3 1 80h to ffh 000
36 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8.3.1 set rswp setting the rswp is enabled by sending the set rswp command, similar to a normal write command to the device which programs the write protection to the target quadrant. the set rswp sequence requires sending a control byte of ?0110mmm0? (where the ?m? represents the memory quadrant identifier for the target quadrant to be write-protected) with the r/ w bit set to a logic 0. in conjunction with sending the protocol, the a 0 pin must be connected to v hv for the duration of rswp sequence (see figure 8-7 and table 8-5 ). the set rswp command acts on a single quadrant only as specified in the set rswp command and can only be reversed by issuing the clear rswp command and will unprotect all quadrants in one operation (see table 8-4 ). example: if quadrant 0 and quadrant 3 are to be write-protected, two separate set rswp commands would be required; however, only one clear rswp command is needed to clear and unprotect both quadrants. table 8-4. set rswp and clear rswp notes: 1. x = don?t care but recommend to be hard-wired to v cc or gnd. 2. see table 8-5 for v hv values. 3. due to the requirement for the a0 pin to be driven to v hv , the set rswp and clear rswp commands are fully supported in a single dimm (isolated dimm) end application or single dimm programming station only. table 8-5. v hv figure 8-7. set rswp and clear rswp function pin control byte device type identifier memory quadrant identifier r/ w a 2 a 1 a 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 set rswp, quadrant 0 x x v hv 0 1 1 0 0 0 1 0 set rswp, quadrant 1 x x 1 0 0 0 set rswp, quadrant 2 x x 1 0 1 0 set rswp, quadrant 3 x x 0 0 0 0 clear rswp x x 0 1 1 0 test condition min max units v hv v hv - v cc 4.8v 7 10 v scl sda start by master ack from slave ack or nack from slave stop by master ack or nack from slave control byte word address byte data word 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 1 1 0 m m m 0 0 x x x x x x x x 0/1 x x x x x x x x 0/1 msb msb msb x = don?t care m = memory quadrant identifier
37 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8.3.2 clear rswp similar to the set rswp command, the reversible write protection on all quadrants can be reversed or unprotected by transmitting the clear rswp command. the clear rswp sequence requires the master to send a start condition followed by sending a control byte of ?01100110? (66h) with the r/ w bit set to a logic 0. the at30tse004 should respond with an ack. the master transmits a word address byte and data bytes with don?t care values. the at30tse004 will respond with either an ack or nack to both the word address and data word. in conjunction with sending the protocol, the a 0 pin must be connected to v hv for the duration of the clear rswp command (see figure 8-7 and table 8-5 ). to end the clear rswp sequence, the master sends a stop condition. caution: the write protection of individual quadrants cannot be reversed separately, and executing the clear rswp command will clear the write protection on all four quadrants leaving all quadrants with no software write protection. 8.3.3 read rswp the read rswp command allows the ability to check a quadrant?s write protection status. to find out if the software write protection has been set to a specific quadrant, the same procedure that was used to set the quadrant?s write protection can be utilized except that the r/ w select bit is set to a logic 1, and the a 0 pin is not required to have v hv (see table 8-7 ). the read rswp sequence requires sending a control byte of ?0110mmm1? (where the ?m? represents the memory quadrant identifier for the quadrant to be read) with the r/ w bit set to a logic 1 (see figure 8-8 ). if the rswp has not been set, then the at30tse004 responds to the control byte with an ack, and responds to the word address byte and data word with a nack. if the rswp has been set, the at30tse004 responds to all three bytes (control, word address and data bytes) with a nack as shown in table 8-6 . table 8-6. serial eeprom acknowledge when reading protection status table 8-7. read rswp notes: 1. x= don?t care but recommend to be hard-wired to v cc or gnd. 2. see table 8-5 for v hv values. quadrant status instruction sent instruction response word address sent word address response data word sent data word response write protected read rswp nack don?t care nack don?t care nack not protected read rswp ack don?t care nack don?t care nack function pin control byte device type identifier memory quadrant identifier r/ w a 2 a 1 a 0 b7 b6 b5 b4 b3 b2 b1 b0 read rswp, quadrant 0 x x 0, 1 or v hv 0 1 1 0 0 0 1 1 read rswp, quadrant 1 x x 1 0 0 1 read rswp, quadrant 2 x x 1 0 1 1 read rswp, quadrant 3 x x 0 0 0 1
38 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 figure 8-8. read rswp 8.4 serial eeprom read operations all read operations are initiated by the master transmitting a start bit, a device type identifier of ?1010? (ah), three software address bits (a2, a1, a0) that match their corresponding hard-wired address pins (a 2 , a 1 , a 0 ), and the r/ w select bit with a logic 1 state. in the following clock cycle, the device should respond with an ack. the subsequent protocol depends on the type of read operation desired. there are three read operations: current address read, random address read, and sequential read. caution: all read operations should be preceded by the spa and or rpa commands to ensure the desired half of the memory is selected. the reason this is important, for example, during a sequential read operation on the last byte in the first half of the memory (address ffh) with spa=0 (indicating first half is selected), the internal address counter will roll-over to address 00h in the first half of memory as opposed to the first byte in the second half of the memory. for more information on the spa and rpa commands, see section 8.1.1 ?set page address and read page address commands? on page 29 . 8.4.1 current address read following a start condition, the master only transmits the device address byte with the r/ w select bit set to a logic 1 (see figure 8-9 ). the at30tse004 should respond with an ack and then serially transmits the data word addressed by the internal address counter. the internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. this address stays valid between operations as long as power to the device is maintained. the address roll-over during a read is from the last byte of the last page to the first byte of the first page of the addressed 2-kbit (depends on the current spa setting). to end the command, the master does not respond with an ack but does generate a following stop condition. figure 8-9. current address read from serial eeprom sck sda start by master ack or nack from slave nack from master stop by master nack from master control byte word address byte data byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 0 1 1 0 m m m 1 0/1 x x x x x x x x 1 x x x x x x x x 1 msb msb msb x = don?t care m = memory quadrant identifier scl sda device address byte data word (n) start by master ack from slave nack from master stop by master msb msb 1 0 1 0 a2 a1 a0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
39 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8.4.2 random read a random read operation allows the master to access any memory location in a random manner and requires a dummy write sequence to preload the starting data word address. to perform a random read, the device address byte and the word address byte are transmitted to the at30tse004 as part of the dummy write sequence (see figure 8-10 ). once the device address byte and data word address are clocked in and acknowledged by the at30tse004, the master must generate another start condition. the master initiates a current address read by sending another device address byte with the r/ w select bit to a logic 1. the at30tse004 acknowledges the device address byte, increments its internal address counter and serially clocks out the first data word. the device will continue to transmit sequential data words as long as the master continues to ack each data word. to end the sequence, the master responds with a nack and a stop condition. figure 8-10. random read from serial eeprom scl sda start by master ack from slave ack from slave device address byte word address byte msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a2 a1 a0 0 0 0 dummy write start by master ack from slave nack from master device address byte data word (n) stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a2 a1 a0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 1 a7 a6 a5 a4 a3 a2 a1 a0
40 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 8.4.3 sequential read a sequential read operation is initiated in the same way as a random read operation, except after the at30tse004 transmits the first data word, the master responds with an ack (instead of a nack followed by a stop condition). as long as the at34tse004 receives an ack, it will continue to increment the data word address and serially clock out the sequential data words (see figure 8-11 ). when the internal address counter is at the last byte of the last page, the data word address will roll-over to the beginning of the selected 2-kbit array (depending on the spa setting) starting at address zero, and the sequential read operation will continue. the sequential read operation is terminated when the master responds with a nack followed by a stop condition. figure 8-11. sequential read from serial eeprom scl sda start by master ack from slave ack from master device address byte data word (n) msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 1 0 a2 a1 a0 1 0 d7 d6 d5 d4 d3 d2 d1 d0 0 ack from master nack from master stop by master ack from master data word (n+1) data word (n+2) data word (n+x) 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 0 d7 d6 d5 d4 d3 d2 d1 d0 1 msb msb msb
41 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 9. part marking detail 9.1 part markings drawing no. rev. title 30tse004 e 8/17/12 30tse004sm , at30tse004 package marking information package mark contact: dl-cso-assy_eng@atmel.com at30tse004: package marking information catalog number truncation at30tse004 truncation code ###: t8 date codes voltages y = year m = month ww = work week of assembly % = minimum voltage 2: 2012 6: 2016 a: january 02: week 2 m: 1.7v min 3: 2013 7: 2017 b: february 04: week 4 4: 2014 8: 2018 ... ... 5: 2015 9: 2019 l: december 52: week 52 country of assembly lot number grade/lead finish material @ = country of assembly aaa...a = atmel wafer lot number 5: industrial (-20c to 125c) nipdau trace code atmel truncation xx = trace code (atmel lot numbers correspond to code) at: atmel example: aa, ab.... yz, zz atm: atmel atml: atmel 8-lead udfn t8 5m@ yxx 2.0 x 3.0 mm body note 2: package drawings are not to scale note 1: designates pin 1 8-lead wdfn t8 5m@ yxx 2.0 x 3.0 mm body
42 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 10. ordering information 10.1 ordering code detail at30tse004-ma5m-t atmel designator product family device density shipping carrier option device grade package option 4 = 4-kilobit 30tse = digital temperature sensor with integrated eeprom b = bulk (tubes) t = tape and reel 5 = green, nipdau lead finish temperature range (-20c to +125c) ma = 8-lead, 2 x 3 x 0.6mm (udfn) maa = 8-lead, 2 x 3 x 0.8mm (wdfn) sensor type m = 1.7v to 3.6v voltage option
43 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 11. green package options (pb/halide-free/rohs compliant) note: 1. consistent with the general semiconductor market trend, atmel will supply devices with either gold or cop- per bond wires to increase manufacturing flexibility and ensure a long-term continuity of supply. there is no difference in product quality, reliability, or performance between the two variations. 2. t = tape and reel ? udfn and wdfn= 5k per reel ordering code (1) package lead finish operating voltage max. frequency operational range at30tse004-ma5m-t (2) 8ma2 nipdau 1.7v to 3.6v 1000khz ?20 ? c to 125 ? c at30tse004-maa5m-t (2) 8maa package type 8ma2 8-lead, 2 x 3 x 0.6mm, thermally enhanced plastic ultra thin dual flat no lead package (udfn) 8maa 8-lead, 2 x 3 x 0.8mm, thermally enhanced plastic very very thin dual flat no lead package (wdfn)
44 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 12. package drawing 12.1 8ma2 ? 8-lead udfn title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 8ma2 ynz c 8ma2, 8-pad, 2 x 3 x 0.6 mm body, thermally enhanced plastic ultra thin dual flat no lead package (udfn) common dimensions (unit of measure = mm) symbol min nom max note d 1.90 2.00 2.10 e 2.90 3.00 3.10 d2 1.40 1.50 1.60 e2 1.20 1.30 1.40 a 0.50 0.55 0.60 a1 0.0 0.02 0.05 a2 ? ? 0.55 c 0.152 ref l 0.30 0.35 0.40 e 0.50 bsc b 0.18 0.25 0.30 3 k 0.20 ? ? 9/6/12 d2 e2 e e (6x) l (8x) b (8x) pin#1 id a a1 a2 pin 1 id d c k 8 7 6 5 1 2 3 4 1 2 3 4 8 7 6 5
45 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 12.2 8maa ? 8-lead wdfn drawing no. rev. title gpc 8maa a 09/11/12 8maa, 8-pad 2.0 x 3.0mm body, 0.50mm pitch very, very thin dual no lead package (wdfn) (sawn) yrv common dimensions (unit of measure = mm) symbol min nom max note a 0.70 0.75 0.80 a1 0.00 0.02 0.05 a2 0.45 0.55 0.65 a3 2.0 ref d 1.90 2.00 2.10 d2 1.20 - 1.60 e 2.90 3.00 3.10 e2 1.20 - 1.60 b 0.18 0.25 0.30 2 l 0.30 ? 0.45 e 0.50 bsc top view side view bottom view package drawing contact: packagedrawings@atmel.com notes: 1. this drawing is for general information only. refer to jedec drawing mo-229, wced-3, for proper dimensions, tolerances, datums, etc. 2. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 3. soldering the large thermal pad is optional, but not recommended. no electrical connection is accomplished to the device through this pad, so if soldered it should be tied to ground a2 b (8x) pin 1 id pin 1 index area a1 a3 d e a l (8x) e (6x) 1.50 ref. d2 e2
46 atmel at30tse004 [preliminary datasheet] 8816b?dts?12/2012 13. revision history functionzz_summary notes doc. rev. date comments 8816b 04/2013 not recommended for new designs. replaced by at30tse004a. 8816b 12/2012 increase v por maximum from 1.5v to 1.6v. decrease t i 100khz maximum from 100ns to 50ns. minor text changes to dc, ac, and termperature sensor characteristics tables. 8816a 09/2012 initial document release.
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